Concurrent error-detectable butterfly chip for real-time FFT processing through time redundancy

The chip design for a fast Fourier transform (FFT) butterfly module using a novel concurrent error detection (CED) technique is presented. It is a time-redundant realization based on the direct complex computation approach. By the use of symmetry and the exchanging design strategy, the recomputation step can be performed by interleaving the circuits for the real and imaginary parts in a complex function. It leads to a lower hardware overhead (about 7/(4n+8), where n is the word length), and the error detection capability is as robust as that of the duplicated module technique. The CED butterfly is designed in 1.2-μm CMOS technology, using the structural silicon complier. The theoretical analysis and experimental results are presented. It is shown that the design is very attractive for real-time high-reliability DSP systems. Its regular structure make the proposed algorithm and architecture easy to implement in VLSI or WSI