70-MHz 2-μm CMOS bit-level systolic array median filter

Author

Roncella, Roberto ; Saletti, Roberto ; Terreni, Pierangelo

Author_Institution

Dipartimento di Ingegneria dell´´Inf. Elettronica, Pisa Univ., Italy

Volume

28

Issue

5

fYear

1993

fDate

5/1/1993 12:00:00 AM

Firstpage

530

Lastpage

536

Abstract

An algorithm for VLSI median filtering of one-dimensional signals of complexity linearly dependent on the filter window length is described. The algorithm is implemented as a bit-level systolic array (BLSA), in order to achieve high performance. A single-chip median filter characterized by a window length of 25 8-b samples, and by operation on three interleaved independent sequences for a total of 75 samples, is presented as a demonstration of the concept. The throughput relevant to one sequence is 1/3 for this chip, whereas the theoretical maximum allowed by the algorithm is 1/2. Prototypes designed with a 2-μm CMOS technology have been successfully tested at a clock frequency over 70 MHz

Keywords

CMOS integrated circuits; VLSI; digital filters; digital signal processing chips; pipeline processing; systolic arrays; 2 micron; 70 MHz; CMOS technology; VLSI median filtering; bit-level systolic array; filter window length; filtering algorithm; interleaved independent sequences; median filter; one-dimensional signals; single-chip; CMOS technology; Clocks; Filtering algorithms; Filters; Frequency; Prototypes; Systolic arrays; Testing; Throughput; Very large scale integration;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.229403

Filename

229403