Logic drive circuit for 3-phase charge-coupled devices

A simple logic circuit is escribed which acts as a modulo-3 ring counter and provides three driving phases suitable to operate a 3-phase c.c.d. The circuit is driven by a clock, the rate of which corresponds to three times the desired element rate in the c.c.d. The pulsewidth of the clock determines the amount of mutual overlap between subsequent phases. An additional gating input permits stopping the counter in a predetermined state, such as would be required to switch a c.c.d. into the integration mode. The circuit contains only 12 gates, and when implemented with a t.t.l. high-speed logic component runs up to input clock rates of 50 MHz.