Exploiting Domain Knowledge in IC Cell Layout

This article describes a knowledge-based expert system, Talib, whose domain of expertise is in the cell layout phase of the IC design task. It applies Al techniques and has been used to design IC layouts in the circuit range of four to 86 transistors. The system is implemented in OPS5, a general-purpose rule-based language. Talib accepts as input the schematic of the proposed circuit along with the description of the cell layout boundary, and produces as output the description of the mask geometry in CalTech Intermediate Form. The cell layout problem is based on a single metal, single polysilicon, NMOS process. It is further constrained to be in the framework of Manhattan geometry, hence only orthogonal lines are used.