Title :
Memory testing by linear checks
Author_Institution :
Boston University, System and Electrical Engineering, College of Engineering, Department of Computers, Boston, USA
fDate :
9/1/1984 12:00:00 AM
Abstract :
In this paper we consider methods of error detection, location or correction in ROM or RAM by systems of orthogonal linear equality and inequality checks and by the Rademacher transform. Implementations and error detecting, locating, correcting capabilities of these techniques for ROM and RAM testing are also described.
Keywords :
error correction; error detection; random-access storage; read-only storage; RAM; ROM; Rademacher transform; error correction; error detection; error location; linear checks; memory testing;
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
DOI :
10.1049/ip-e.1984.0033
