DocumentCode
929905
Title
Digit-pipelined direct digital frequency synthesis based on differential CORDIC
Author
Kang, Chang Yong ; Swartzlander, Earl E., Jr.
Author_Institution
Intel Corp., Chandler, AZ, USA
Volume
53
Issue
5
fYear
2006
fDate
5/1/2006 12:00:00 AM
Firstpage
1035
Lastpage
1044
Abstract
A novel direct digital frequency synthesis (DDFS) architecture based on the differential CORDIC (DCORDIC) algorithm is presented. The architecture allows digit-level pipelining in the CORDIC angle path by implementing a two-dimensional systolic array. Unlike other DDFS architectures, it incorporates the phase accumulator in the digit-level pipelining framework so that a bottleneck-free datapath throughout the whole system is achieved in a scalable manner. A generic environment that generates fully synthesizable Verilog codes that implement the proposed architecture is created and the physical attributes of the resulting system are discussed.
Keywords
digital arithmetic; direct digital synthesis; hardware description languages; logic design; signal processing; systolic arrays; 2D systolic array; Verilog codes; differential CORDIC; digit-level pipelining; direct digital frequency synthesis; online arithmetic; Computer architecture; Digital arithmetic; Frequency synthesizers; Hardware design languages; Iterative algorithms; Oscillators; Pipeline processing; Read only memory; Systolic arrays; Tuning; Digit-level pipelining; differential CORDIC (DCORDIC); direct digital frequency synthesis (DDFS); on-line arithmetic; systolic array;
fLanguage
English
Journal_Title
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher
ieee
ISSN
1549-8328
Type
jour
DOI
10.1109/TCSI.2005.862183
Filename
1629242
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