Implementing precise interruptions in pipelined RISC processors

Pipelining is an implementation technique that exploits parallelism among instructions. Imprecise interruption problems arise when a pipelined processor has multiple multicycle functional units because instruction completion might be out of order. An early issued, long-running instruction might generate an interruption after the completion of several short-running instructions issued later, resulting in an imprecise interruption. Four methods of providing precise interruptions with regard to performance degradation and cost of implementation are compared from the VLSI silicon resources perspective. Results provide valuable information for VLSI processor designers to consider if they include the precise interruption in their designs. The four methods are in-order instruction completion, reorder buffer, history file, and future file.<>