DocumentCode :
929996
Title :
Clock period minimization with wave pipelining
Author :
Joy, Donald A. ; Ciesielski, Maciej J.
Author_Institution :
Massachusetts Univ., Amherst, MA, USA
Volume :
12
Issue :
4
fYear :
1993
fDate :
4/1/1993 12:00:00 AM
Firstpage :
461
Lastpage :
472
Abstract :
A method using a linear program for adjusting clock delays in individual flip-flops to minimize the clock period through the use of wave pipelining is discussed. Edge-triggered flip-flops are used as the circuit memory elements, and controlled delays are introduced in the time of clock signal arrivals at these elements. Constraints that relate the logic path delays from pairs of input flip-flops are derived. These constraints, in addition to known constraints relating input and output flip-flops, prevent destructive logic signal propagation interference. It is shown that in circuits without feedback the clock period reduction is limited by the shortest paths in the logic and the required signal separation between signals of distinct cycles. Application of this technique to logic with feedback is discussed
Keywords :
clocks; delays; feedback; flip-flops; logic design; pipeline processing; synchronisation; clock period minimisation; clock period reduction; controlled delays; edge-triggered type; feedback; flip-flops; linear program; logic path delays; wave pipelining; Clocks; Delay effects; Feedback circuits; Flip-flops; Interference constraints; Logic circuits; Minimization; Pipeline processing; Propagation delay; Source separation;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/43.229730
Filename :
229730
Link To Document :
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