Test generation to minimize error masking

A unified scheme for test-pattern generation and output compaction using circuit-specific information is presented. It is shown that partial control over test-pattern sequence can give zero aliasing in single-output circuits and reduced aliasing in multiple-output circuits. The exact aliasing probability is obtained for multiple-output circuits under the independent bit error model for any test length. The aliasing probability for multiple-output circuits of this scheme is independent of the feedback polynomial of the multiple-input shift register (MISR). This method reduces aliasing considerably without increasing the length of the MISR by having a simple quotient detector. The approach is applied to benchmark circuits to show the applicability of the scheme to a given combinational circuit