Design of an optimised 2.5 GHz CMOS differential LC oscillator

An analytic method to predict the oscillation amplitude and supply current values of a differential CMOS oscillator. A simplified model to predict the phase noise performance for this type of oscillator is developed. Using this method, it becomes possible to design an optimised oscillator in terms of a minimum phase noise and low power consumption. The validity of the method has been verified by designing a LC CMOS oscillator using 0.25 μm CMOS technology. The predictions are in good agreement with simulation results over a wide range of the supply voltage.