Title :
Statistical degradation analysis of digital CMOS IC´s
Author :
Rangavajjhala, Venkata S. ; Bhuva, Bharat L. ; Kerns, Sherra E.
Author_Institution :
Cirrus Logic Inc., Milpitas, CA, USA
fDate :
6/1/1993 12:00:00 AM
Abstract :
A statistical switch-level simulator, based on interval and statistical analysis techniques, that simulates the effects of fabrication process fluctuations and environmental effects on digital CMOS integrated circuits is presented. The simulator is computationally very cost-effective compared to conventional Monte Carlo simulators, yet produces results with equal accuracy. The simulator enables analysis of the sensitivity of critical function and performance levels to a variety of parameter variations, thus providing a basis for establishing correspondence between process control, yield, and reliability
Keywords :
CMOS integrated circuits; circuit analysis computing; digital integrated circuits; failure analysis; integrated logic circuits; statistical analysis; degradation analysis; digital CMOS integrated circuits; environmental effects; fabrication process fluctuations; parameter variations; performance failure; statistical analysis; statistical switch-level simulator; Analytical models; CMOS digital integrated circuits; CMOS integrated circuits; Circuit simulation; Computational modeling; Degradation; Fabrication; Fluctuations; Statistical analysis; Switching circuits;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
