Layout-dependent fault analysis and test synthesis for CMOS circuits

Author

Jacomet, Marcel ; Guggenbühl, Walter

Author_Institution

Dept. of Electron., Sch. of Eng., Biel, Switzerland

Volume

12

Issue

6

fYear

1993

fDate

6/1/1993 12:00:00 AM

Firstpage

888

Lastpage

899

Abstract

An arithmetic approach to extract the potential physical defects from the specific circuit layout of an integrated circuit is proposed. The defects subsequently are transformed into circuit faults and weighted according to their likelihood of occurrence. Based on these open and short faults extracted from CMOS layouts, an automatic test pattern generator is implemented. The test synthesis of some combinational CMOS benchmark circuits illustrates the superiority of the CMOS fault models and their application to test pattern generation as compared with the classical stuck-at fault models

Keywords

CMOS integrated circuits; automatic testing; circuit analysis computing; circuit layout CAD; combinatorial circuits; design for testability; fault location; integrated circuit testing; integrated logic circuits; logic CAD; logic testing; CMOS circuits; FANTESTIC; arithmetic approach; automatic test pattern generator; circuit faults; circuit layout; fault analysis; fault models; integrated circuit; layout dependent methods; physical defects; test synthesis; Arithmetic; Benchmark testing; Circuit faults; Circuit simulation; Circuit synthesis; Circuit testing; Integrated circuit synthesis; Integrated circuit testing; Semiconductor device modeling; Test pattern generators;

fLanguage

English

Journal_Title

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on

Publisher

ieee

ISSN

0278-0070

Type

jour

DOI

10.1109/43.229763

Filename

229763