• DocumentCode
    930483
  • Title

    High-Speed GaAs SDFL Divider Circuit

  • Author

    Walton, Emory R., Jr. ; Shen, Eve K. ; Lee, Frank S. ; Zucca, Ricardo ; Shen, Yie-Der ; Welch, Bryant M. ; Dikshit, Rahul

  • Volume
    30
  • Issue
    7
  • fYear
    1982
  • Firstpage
    1020
  • Lastpage
    1026
  • Abstract
    High-speed divider circuits find numerous applications in prescalers for counters, frequency synthesizers, and digital phase locked loops. To accommodate these applications, a high-speed multimode divider circuit has been designed, fabricated, and tested. This circuit, fabricated on semi-insulating Gallium Arsenide substrates, and utilizing Schottky diode FET logic (SDFL) technology, has been tested at a maximum clock frequency of 1.84 GHz. High yields of circuits operating over 1 GHz have been obtained over a number of wafers.
  • Keywords
    Circuit testing; Clocks; Counting circuits; FETs; Frequency synthesizers; Gallium arsenide; Logic circuits; Logic testing; Phase locked loops; Schottky diodes;
  • fLanguage
    English
  • Journal_Title
    Microwave Theory and Techniques, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9480
  • Type

    jour

  • DOI
    10.1109/TMTT.1982.1131192
  • Filename
    1131192