Title :
High-k gate dielectrics with ultra-low leakage current for sub-45nm CMOS
Author :
Venkateshan, A. ; Singh, R. ; Poole, K.F. ; Harriss, J. ; Senter, H. ; Teague, R. ; Narayan, J.
Author_Institution :
Clemson Univ., Clemson
Abstract :
The results of a new method of high-kappa dielectric formation are reported. For effective oxide thickness of 0.39 nm, the leakage current density of metal-high-kappa-silicon structure is about 1 times 10-12 A/cm2 for gate voltage from +3 to -3 V. The descriptive statistics and process variation data presented demonstrate that the process is robust and manufacturing tools can be developed without any fundamental barrier.
Keywords :
CMOS integrated circuits; elemental semiconductors; high-k dielectric thin films; leakage currents; silicon; CMOS; gate voltage; high-kappa gate dielectrics; metal-high-kappa-silicon structure; oxide thickness; size 0.39 nm; size 45 nm; ultra-low leakage current; voltage 3 V to -3 V;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:20072178
