Title :
A pipelined associated memory implemented in VLSI
Author :
Clark, Lawrence T. ; Grondin, Robert O.
Author_Institution :
Center for Solid State Electron. Res., Arizona State Univ., Tempe, AZ, USA
Abstract :
A memory system which rapidly chooses the stored item most closely matching a given input is fundamental to a number of recognition tasks. A memory architecture which performs this function is discussed. In addition, a measure of the quality of the selected (best matching) memory is generated. The architecture is capable of significant data throughput rates and is amenable to implementation using conventional digital VLSI fabrication process. These characteristics are demonstrated by a prototype device fabricated using the MOSIS 3- mu m CMOS design rules, which can compare more than two million 9-bit input works per second. Behavioral simulations demonstrate the applicability of the architecture to some basic recognition tasks.<>
Keywords :
CMOS integrated circuits; VLSI; content-addressable storage; integrated memory circuits; pattern recognition; pipeline processing; 3 micron; 3 micron design rules; 9 bit; CMOS; MOSIS; VLSI; behavioural simulations; characteristics; conventional digital VLSI fabrication process; data throughput rates; implementation; item most closely matching; memory architecture; pipelined associated memory; prototype device; recognition tasks; Artificial neural networks; CADCAM; Circuits; Computer aided manufacturing; Computer architecture; Fabrication; Impedance matching; Mathematical model; Random access memory; Very large scale integration;
Journal_Title :
Solid-State Circuits, IEEE Journal of
