A built-in Hamming code ECC circuit for DRAMs

Author

Furutani, Kiyoro ; Arimoto, Kazutami ; Miyamoto, Hiroshi ; Kobayashi, Toshifumi ; Yasuda, Ken-Ichi ; Mashiko, Kochiro

Author_Institution

Mitsubishi Electr. Corp., Hyogo, Japan

Volume

24

Issue

1

fYear

1989

Firstpage

50

Lastpage

56

Abstract

An error checking and correcting (ECC) technique that checks multiple cell data simultaneously and allows fast column access is described. The ECC circuit is optimized with respect to the increase in the chip area and the access-time penalty, and can be applied to a 16-Mbit DRAM with 20% chip area increase and less access-time penalty. The soft error rate has been estimated to be about 100 times smaller than that of the basic horizontal-vertical parity-code ECC technique.<>

Keywords

VLSI; automatic testing; error correction codes; integrated circuit technology; integrated circuit testing; integrated memory circuits; random-access storage; 16 Mbit; BIST; DRAM; access-time penalty; built-in Hamming code ECC circuit; checks multiple cell data simultaneously; chip area increase; error checking and correcting; fast column access; horizontal-vertical parity-code ECC technique; soft error rate; Capacitance; Data mining; Decoding; Error analysis; Error correction; Error correction codes; Frequency; Integrated circuit yield; Production; Random access memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.16301

Filename

16301