High-speed CMOS circuit technique

Author

Yuan, Jiren ; Svensson, Christer

Author_Institution

Dept. of Phys. & Meas. Technol., Linkoping Univ., Sweden

Volume

24

Issue

1

fYear

1989

Firstpage

62

Lastpage

70

Abstract

It is shown that clock frequencies in excess of 200 MHz are feasible in a 3- mu m CMOS process. This performance can be obtained by means of clocking strategy, device sizing, and logic style selection. A precharge technique with a true single-phase clock, which increases the clock frequency and reduces the skew problems, is used. Device sizing with the help of an optimizing program improves circuit speed by a factor of 1.5-1.8. The logic depth is minimized to one instead of two or more, and pipeline structures are used wherever possible. Experimental results for several circuits which work at clock frequencies of 200-230 MHz are presented. SPICE simulation shows that some circuits could work up to 400-500 MHz.<>

Keywords

CMOS integrated circuits; digital simulation; integrated circuit technology; integrated logic circuits; logic CAD; 200 to 230 MHz; 3 micron; 3 micron CMOS process; 400 to 500 MHz; SPICE simulation; circuit speed; clock frequencies; clocking strategy; device sizing; high speed CMOS circuit technique; logic depth; logic style selection; optimizing program; pipeline structures; precharge technique; skew problems; true single-phase clock; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Frequency; Latches; Logic devices; Physics; Pipelines; SPICE;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.16303

Filename

16303