Implementation of a parallel-formant speech synthesiser using a single-chip programmable signal processor

A speech quality almost indistinguishable from human speech has already been demonstrated at the Joint Speech Ressearch Unit (JSRU), using a parallel-formant speech synthesiser. Realisations of this synthesiser have incluede an analogue hardware version, and a simulation as a FORTRAN program. The new sampled-data implementation described here performs the calculations required at a sample rate of 10 kHz on a programmable signal processor chip, the NEC ¿PD7720. The total synthesiser system, on a small printed circuit, comprises the signal processor chip, three chips for analogue output and filtering, two chips for timing generatation and a four-chip `feeder¿ computer, which organises the control data into a suitable form. New sets of controls are provided at a 100 Hz rate by some host computer, which organises the control data into a suitable form. New sets of controls are provided at a 100 Hz rate by some host computer, and are interpolated at a 1 kHz rate within the signal processor. The controls are six-bit parameters which specify four formant frequencies, five formant amplitudes, the degree of voicing, the fundamental frequency, and the mark/space ratio of the voiced excitation waveform. For experimental purposes, a control has been added to enable various internal signals in the synthesiser to be observed. The synthesiser has been tested using control signals derived from human speech, but its main application will be with an additional microcomputer to generate speech directly from a linguistic description, by rule.