Digital characteristics of CMOS devices at cryogenic temperatures

The results of measurements of the digital characteristics of CMOS devices as a function of temperature between 77 and 300 K and of supply voltage between 3 and 20 V are presented. Using a fixed supply of 5 V, the low noise margin decreased from 2.54 to 2.11 V, but the high noise margin increased from 2.18 to 2.40 V as the temperature was increased from 77 to 300 K. On lowering the temperature from 300 to 77 K, both V_II and V_IH increased and the transition between these input logic voltages became more abrupt. These and other digital characteristics including noise immunity. V _H-V_I, and V_IH-V _II all showed a smooth monotonic improvement as the temperature decreased. These results can be qualitatively explained due to the increase in the absolute threshold voltages of the NMOS and PMOS transistors and to the decrease in the β_N/β_P ratio as the temperature is lowered