• DocumentCode
    931633
  • Title

    Design methodology for self-timed VLSI systems

  • Author

    Lister, P.F. ; Alhelwani, A.M.

  • Author_Institution
    University of Sussex, School of Engineering and Applied Sciences, Brighton, UK
  • Volume
    132
  • Issue
    1
  • fYear
    1985
  • fDate
    1/1/1985 12:00:00 AM
  • Firstpage
    25
  • Lastpage
    32
  • Abstract
    A design methodology for self-timed VLSI systems is proposed. This includes a language for describing algorithmic behaviour which is based on the data-flow concept. A subclass of Petri nets is introduced to model the designed system, and a refinement technique is presented that allows for the synthesis of correct-by-construction systems. Finally, a systematic means for implementing the design is given.
  • Keywords
    VLSI; directed graphs; logic design; parallel processing; specification languages; Petri nets; algorithmic-behavioural description language; correct-by-construction systems; data-flow concept; design methodology; refinement technique; self-timed VLSI systems; subclass;
  • fLanguage
    English
  • Journal_Title
    Computers and Digital Techniques, IEE Proceedings E
  • Publisher
    iet
  • ISSN
    0143-7062
  • Type

    jour

  • DOI
    10.1049/ip-e:19850003
  • Filename
    4646400
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=931633