Title :
A 700-MHz 24-b pipelined accumulator in 1.2-μm CMOS for application as a numerically controlled oscillator
Author :
Lu, Fang ; Samueli, Henry ; Yuan, Jiren ; Svensson, Christer
Author_Institution :
Broadband Telecom Inc., Los Angeles, CA, USA
fDate :
8/1/1993 12:00:00 AM
Abstract :
To accomplish timing recovery/synthesis in high-speed communication systems, a 24-b numerically controlled oscillator (NCO) IC using a circuit design technique called true single-phase clock (TSPC) pipelined CMOS has been fabricated in a standard 1.2-μm CMOS process. The device achieves a maximum tested input clock rate of 700 MHz, which results in an output frequency tuning range from DC up to 350 MHz with a 41.7-Hz tuning resolution and a peak-to-peak phase jitter of 1.4 ns. The 1.7-mm×1.7-mm IC dissipates 850 mW with a single 5-V supply, which is substantially lower than similar ECL and GaAs devices
Keywords :
CMOS integrated circuits; digital integrated circuits; numerical control; pipeline processing; synchronisation; tuning; variable-frequency oscillators; 0 to 350 MHz; 1.2 micron; 1.7 mm; 24 bit; 5 V; 700 MHz; 850 mW; CMOS process; IC; high-speed communication systems; numerically controlled oscillator; output frequency tuning range; pipelined CMOS; pipelined accumulator; single 5-V supply; timing recovery/synthesis; true single-phase clock; CMOS integrated circuits; CMOS process; Circuit optimization; Circuit synthesis; Clocks; Communication system control; Control system synthesis; Oscillators; Timing; Tuning;
Journal_Title :
Solid-State Circuits, IEEE Journal of
