DocumentCode :
931819
Title :
An I2L clocked gate array for undergraduate design exercises
Author :
Jesshope, Chris R. ; Ashburn, P.
Author_Institution :
University of Southampton, Department of Electronics and Information Engineering, Southampton, UK
Volume :
132
Issue :
2
fYear :
1985
fDate :
3/1/1985 12:00:00 AM
Firstpage :
54
Lastpage :
61
Abstract :
The design of a gate array chip and process suitable for carrying out integrated circuit design exercises at an undergraduate level is described. The array uses simplicity in both processes and design in order to make these exercises economically feasible. The educational value in the exercise is in introducing the students to process design rules and their interpretation. Also it will teach, in a practical manner, the advantages and disadvantages of a gate array implementation for a given logic system. Integrated injection logic is chosen as the technology because of its simplicity and its inherent suitability for realising gate arrays. The novel features of this process are described. The chip architecture is also described in relation to the constraints on in-house design and processing. It is designed as a multiproject chip, where each project has available ten edge-triggered D-types, 54 three output gate and 20 user pads. A typical design example is given together with the projected timescales for the exercise.
Keywords :
cellular arrays; circuit CAD; integrated circuits; integrated injection logic; I2L clocked gate array; design rules; gate array chip; integrated circuit design; multiproject chip; undergraduate design exercises;
fLanguage :
English
Journal_Title :
Computers and Digital Techniques, IEE Proceedings E
Publisher :
iet
ISSN :
0143-7062
Type :
jour
DOI :
10.1049/ip-e.1985.0008
Filename :
4646422
Link To Document :
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