DocumentCode
931826
Title
The use of stabilized CMOS delay lines for the digitization of short time intervals
Author
Rahkonen, Timo E. ; Kostamovaara, Juha T.
Author_Institution
Dept. of Electr. Eng., Oulu Univ., Finland
Volume
28
Issue
8
fYear
1993
fDate
8/1/1993 12:00:00 AM
Firstpage
887
Lastpage
894
Abstract
The basic advantages and limitations of using integrated digital CMOS delay lines for the digitization of short time intervals are discussed. Accuracies of 6-7 b and single-shot resolutions from 0.1 to 10 ns are demonstrated to be realizable using fully integrated, tapped, and voltage-controlled CMOS delay lines as a time base for the measurement
Keywords
CMOS integrated circuits; delay lines; digital integrated circuits; stability; time measurement; 0.1 to 10 ns; digitization; measurement; short time intervals; single-shot resolutions; stabilized CMOS delay lines; voltage-controlled; CMOS logic circuits; Clocks; Delay effects; Delay lines; Flip-flops; Frequency; Interpolation; Pulse measurements; Time measurement; Timing;
fLanguage
English
Journal_Title
Solid-State Circuits, IEEE Journal of
Publisher
ieee
ISSN
0018-9200
Type
jour
DOI
10.1109/4.231325
Filename
231325
Link To Document