Title :
Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style
Author :
Mahmoodi-Meimand, Hamid ; Roy, Kaushik
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fDate :
3/1/2004 12:00:00 AM
Abstract :
A leakage-tolerant design technique for high fan-in dynamic logic circuits is presented. An NMOS transistor with gate and drain terminals tied together (diode) is added in series with the evaluation network of standard domino circuits. Due to the stacking effect, the leakage of the evaluation path significantly decreases, thereby improving the robustness of the circuit against deep-submicron subthreshold leakage and input noise. To improve the speed of the circuit, a current mirror is also employed in the evaluation network to increase the evaluation current. The proposed technique (diode-footed domino) exhibits considerable improvement in leakage and noise immunity as compared to the standard domino circuits. Simulation results of wide fan-in gates designed using Berkeley Predictive Technology Models of 70-nm technology demonstrate at least 1.9× noise-immunity improvement at the same delay compared to the standard domino circuits. Dynamic comparators and multiplexers are designed using the diode-footed domino and conventional techniques to demonstrate the effectiveness of the proposed scheme in improving leakage-tolerance and performance of high fan-in circuits.
Keywords :
CMOS logic circuits; leakage currents; logic CAD; logic circuits; Berkeley predictive technology models; NMOS transistor; circuit simulation; circuit speed; current mirror; deep-submicron subthreshold leakage; diode-footed domino; domino circuit network; dynamic comparators; dynamic multiplexers; evaluation current; evaluation network; evaluation path leakage; high fan-in dynamic logic circuits; input noise; leakage immunity; leakage-tolerant design; noise immunity; stacking effect; wide fan-in gates; Circuit noise; Circuit synthesis; Diodes; Logic circuits; MOSFETs; Mirrors; Noise robustness; Predictive models; Stacking; Subthreshold current;
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
DOI :
10.1109/TCSI.2004.823665
