DocumentCode :
932045
Title :
An improved pipelined MSB-first add-compare select unit structure for Viterbi decoders
Author :
Parhi, Keshab K.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA
Volume :
51
Issue :
3
fYear :
2004
fDate :
3/1/2004 12:00:00 AM
Firstpage :
504
Lastpage :
511
Abstract :
Convolutional codes are widely used in many communication systems due to their excellent error-control performance. High-speed Viterbi decoders for convolutional codes are of great interest for high-data-rate applications. In this paper, an improved most-significant-bit (MSB) -first bit-level pipelined add-compare select (ACS) unit structure is proposed. The ACS unit is the main bottleneck on the decoding speed of a Viterbi decoder. By balancing the settling time of different paths in the ACS unit, the length of the critical path is reduced as close as possible to the iteration bound in the ACS unit. With the proposed retimed structure, it is possible to decrease the critical path of the ACS unit by 12% to 15% compared with the conventional MSB-first structures. This reduction in critical path can reduce the level of parallelism (and area) required for a very high-speed Viterbi decoder.
Keywords :
Viterbi decoding; convolutional codes; logic circuits; pipeline arithmetic; communication systems; convolutional codes; critical path length; error-control performance; high-data-rate applications; high-speed Viterbi decoders; iteration bound; most-significant-bit first bit-level pipelined add-compare select unit structure; pipelined MSB-first add-compare select unit structure; Arithmetic; Convolutional codes; Feedback loop; Hardware; Helium; Iterative decoding; Parallel processing; Pipeline processing; Viterbi algorithm;
fLanguage :
English
Journal_Title :
Circuits and Systems I: Regular Papers, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-8328
Type :
jour
DOI :
10.1109/TCSI.2004.823657
Filename :
1275597
Link To Document :
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