Review of built-in test methodologies for gate arrays

The paper presents a review of current and proposed test methodologies for semicustom gate arrays. The necessity of high quality testing is emphasised by considering some of the hazards and penalties associated with poor testability. The usefulness and limitations of testability analysis programs are then considered. A built-in test is introduced as an attractive alternative to conventional approaches based on automatic test pattern generation for highly structured circuits. This test technique is shown to offer significant benefits, including reduced test data volume, improved test quality, and easier maintenance testing. The advantages and disadvantages of three built-in test implementations for gate arrays are discussed. First, an architecture which combines an ad hoc design for testability with a comprehensive on-chip maintenance system is reviewed. This is followed by a presentation of an LSSD-based pseudorandom self-test and the associated test problems. Finally an exhaustive test, based on a similar architecture achieves a high quality test with guaranteed fault coverage. In conclusion, the future direction of test strategy development is predicted, in the context of increasing integration density and the convergence of `semicustom¿¿ and `full-custom¿¿ design styles.