Testability and self-test in NMOS and CMOS VLSI signal processors

The paper presents a system of random pattern/signature analysis self-test in NMOS bit-serial signal processing chips, designed by a silicon compiler. Fault coverage is very high, and is determined without full fault simulation. A trial design shows that the cost in silicon, power, complexity and design difficulty is extremely low. A hierarchical system test can be performed, thus permitting fault tolerance. A dynamic CMOS design style supersedes that of the NMOS bit-serial cells. The problem of generating tests for stuck-open faults is removed. This is proved analytically and fault simulation results are presented.