Organization of the Motorola 88110 superscalar RISC microprocessor

Author

Diefendorff, Keith ; Allen, M.

Author_Institution

Motorola Inc., Austin, TX, USA

Volume

12

Issue

2

fYear

1992

fDate

4/1/1992 12:00:00 AM

Firstpage

40

Lastpage

63

Abstract

Motorola´s second-generation RISC microprocessor, which uses advanced techniques for exploiting instruction-level parallelism, including superscalar instruction issue, our-of-order instruction completion, speculative execution, dynamic instruction rescheduling, and two parallel, high-bandwidth, on-chip caches, is discussed. The microprocessor was designed to serve as the central processor in low-cost personal computers and workstations, and support demanding graphics and digital signal processing applications. The 88110´s instruction set architecture, instruction sequencer, register files, execution units, address translation facilities, caches, and external bus interface are described.<>

Keywords

microprocessor chips; reduced instruction set computing; Motorola 88110; RISC microprocessor; instruction sequencer; instruction set architecture; instruction-level parallelism; register files; Application software; Computer architecture; Computer graphics; Digital signal processing; Microcomputers; Microprocessors; Parallel processing; Reduced instruction set computing; Signal design; Workstations;

fLanguage

English

Journal_Title

Micro, IEEE

Publisher

ieee

ISSN

0272-1732

Type

jour

DOI

10.1109/40.127582

Filename

127582