DocumentCode :
933683
Title :
Low-Latency Factorization Architecture for Algebraic Soft-Decision Decoding of Reed–Solomon Codes
Author :
Ma, Jun ; Vardy, Alexander ; Wang, Zhongfeng
Author_Institution :
Univ. of California, San Diego
Volume :
15
Issue :
11
fYear :
2007
Firstpage :
1225
Lastpage :
1238
Abstract :
Bivariate polynomial factorization is an important stage of algebraic soft-decision decoding of Reed-Solomon (RS) codes and contributes to a significant portion of the overall decoding latency. With the exhaustive search-based root computation method, factorization latency is dominated by the root computation step, especially for RS codes defined over very large finite fields. The root-order prediction method proposed by Zhang and Parhi only improves average latency, but does not have any effect on the worst-case latency of the factorization procedure. Thus, neither approach is well-suited for delay-sensitive applications. In this paper, a novel architecture based on direct root computation is proposed to greatly reduce the factorization latency. Direct root computation is feasible because in most practical applications of algebraic soft-decision decoding of RS codes, enough decoding gain can be achieved with a relatively low interpolation cost, which results in a bivariate polynomial with low Y-degree. Compared with existing works, not only does the new architecture have a significantly smaller worst-case decoding latency, but it is also more area efficient since the corresponding hardware for routing polynomial coefficients is eliminated.
Keywords :
Reed-Solomon codes; algebraic codes; matrix decomposition; polynomial approximation; Reed-Solomon codes; algebraic soft-decision decoding; bivariate polynomial factorization; direct root computation; low-latency factorization architecture; search-based root computation method; Computer architecture; Costs; Decoding; Delay; Galois fields; Hardware; Interpolation; Prediction methods; Reed-Solomon codes; Routing; Direct root computation; Reed–Solomon (RS) decoding; factorization architecture;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2007.904173
Filename :
4351979
Link To Document :
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