Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects

Author

Maheshwari, Atul ; Burleson, Wayne

Author_Institution

Intel Corp., Hillsboro

Volume

15

Issue

11

fYear

2007

Firstpage

1239

Lastpage

1244

Abstract

In this paper, hybrids based on current-sensing and repeaters are proposed for on-chip interconnects in an effort to overcome the limitations of these techniques. A novel receiver for current-sensing results in static power savings and allows an easier transition from current-sensing to traditional full rail voltage signals. Measurements of hybrids on a 0.18-m CMOS technology show significant gains over repeater insertion in delay across wire lengths. Hybrids can also be used in placement constrained and low-noise scenarios to achieve delay and power benefits.

Keywords

CMOS integrated circuits; delays; integrated circuit interconnections; network-on-chip; power consumption; repeaters; CMOS technology; current-sensing technique; delay; low-noise scenarios; on-chip interconnects; receiver; repeater hybrid circuit technique; static power saving; CMOS technology; Capacitance; Delay; Integrated circuit interconnections; Logic; Rails; Repeaters; Very large scale integration; Voltage; Wire; Low-swing signaling; placement constraint; static power;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/TVLSI.2007.904109

Filename

4351980