DocumentCode :
933702
Title :
An Overview of a Compiler for Mapping Software Binaries to Hardware
Author :
Mittal, Gaurav ; Zaretsky, David ; Tang, Xiaoyong ; Banerjee, Prith
Author_Institution :
Univ. of Illinois, Chicago
Volume :
15
Issue :
11
fYear :
2007
Firstpage :
1177
Lastpage :
1190
Abstract :
As new applications in embedded communications and control systems push the computational limits of digital signal processing (DSP) functions, there will be an increasing need for software applications to be migrated to hardware in the form of a hardware-software codesign system. In many cases, access to the high-level source code may not be available. It is thus desirable to have a technology to translate the software binaries intended for processors to hardware implementations. This paper provides details on the retargetable FREEDOM compiler. The compiler automatically translates DSP software binaries to register-transfer level (RTL) VHDL and Verilog for implementation on field-programmable gate arrays (FPGAs) as standalone or system-on-chip implementations. We describe the underlying optimizations and some novel algorithms for alias analysis, data dependency analysis, memory optimizations, procedure call recovery, and back-end code scheduling. Experimental results on resource usage and performance are shown for several program binaries intended for the Texas Instruments C 6211 DSP (VLIW) and the ARM 922 T reduced instruction set computer (RISC) processors. Implementation results for four kernels from the Simulink demo library and others from commonly used DSP applications, such as MPEG-4, Viterbi, and JPEG are also discussed. The compiler generated RTL code is mapped to Xilinx Virtex II and Altera Stratix FPGAs. We record overall performance gains of 1.5-26.9 for the hardware implementations of the kernels. Comparisons with the power aware compiler techniques (PACT) high-level synthesis compiler are used to show that software binaries can be used as intermediate representations from any high-level language and generate efficient hardware implementations.
Keywords :
digital signal processing chips; field programmable gate arrays; hardware description languages; hardware-software codesign; program compilers; reduced instruction set computing; system-on-chip; DSP functions; FPGA; PACT; RISC; Verilog; alias analysis; back-end code scheduling; data dependency analysis; digital signal processing; embedded communications; field-programmable gate arrays; mapping software binaries; memory optimizations; power aware compiler techniques; procedure call recovery; reduced instruction set computer; register-transfer level VHDL; retargetable FREEDOM compiler; system-on-chip implementations; Algorithm design and analysis; Application software; Communication system control; Control systems; Data analysis; Digital signal processing; Embedded computing; Field programmable gate arrays; Hardware; Kernel; Binary translation; compiler; decompilation; hardware-software codesign; high-level synthesis; reconfigurable computing;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/TVLSI.2007.904095
Filename :
4351981
Link To Document :
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