Title :
Fully integrated SONOS flash memory cell array with BT (body tied)-FinFET structure
Author :
Sung, Suk-Kang ; Kim, Tae-Yong ; Cho, Eun Suk ; Cho, Hye Jin ; Choi, Byung Yong ; Oh, Chang Woo ; Cho, Byung-Kyu ; Lee, Choong-Ho ; Park, Donggun
Author_Institution :
Device Res. Team, Samsung Electron. Co., Gyeonggi-Do, South Korea
fDate :
5/1/2006 12:00:00 AM
Abstract :
Fully integrated SONOS memory cell arrays with BT (body tied)-FinFET structure have been fabricated successfully by using manufacturable NOR flash technology. The uniformity of threshold voltage (Vth) distribution of the fabricated FinFET SONOS cells is fairly better than that of conventional flash cells thanks to both the widening effective channel width of FinFET structure and negligible coupling interference of SONOS device. New two-step channel implantation process has been introduced for the compensation for the boron out-diffusion of a three-dimensional silicon fin structure. The measured FinFET SONOS cells with a two-step channel doping profile show the improved program and erase characteristics. For the improvement of program/erase and retention characteristics all together, we have investigated the modulation of erase bias condition with respect to back tunneling effect.
Keywords :
MOSFET; doping profiles; elemental semiconductors; flash memories; integrated memory circuits; random-access storage; silicon; FinFET SONOS cells; NOR flash technology; Si; body tied-FinFET structure; boron out-diffusion; coupling interference; fully integrated SONOS flash memory cell array; program-erase characteristics; three-dimensional silicon fin structure; threshold voltage distribution; two-step channel doping profile; two-step channel implantation process; Boron; Doping profiles; FinFETs; Flash memory cells; Interference; Manufacturing; Modulation coding; SONOS devices; Silicon; Threshold voltage; Erase; FinFET; NOR flash; SONOS; program; retention; threshold voltage;
Journal_Title :
Nanotechnology, IEEE Transactions on
DOI :
10.1109/TNANO.2006.869954