DocumentCode :
933903
Title :
Semicustom Design Methodology of Power Gated Circuits for Low Leakage Applications
Author :
Kim, Hyung-Ock ; Shin, Youngsoo
Author_Institution :
Korea Adv. Inst. of Sci. & Technol., Daejeon
Volume :
54
Issue :
6
fYear :
2007
fDate :
6/1/2007 12:00:00 AM
Firstpage :
512
Lastpage :
516
Abstract :
The application of power gating to cell-based semi- custom design typically calls for customized cell libraries, which incurs substantial engineering efforts. In this brief, a semicustom design methodology for power gated circuits that allows unmodified conventional standard-cell elements is proposed. In particular, a new power network architecture is proposed for cell-based power gating circuits. The impact of body bias on current switch design and the layout method of current switch for flexible placement are investigated. The circuit elements that supplement cell-based power gating design are then discussed, including output interface circuits and state retention flip-flops. The proposed methodology is applied to ISCAS benchmark circuits and to a commercial Viterbi decoder with 0.18-mum CMOS technology.
Keywords :
CMOS logic circuits; flip-flops; integrated circuit layout; logic design; CMOS technology; Viterbi decoder; cell-based power gating circuits; low leakage applications; output interface circuits; power gated circuits; power network architecture; semicustom design methodology; size 0.18 mum; state retention flip-flops; unmodified conventional standard-cell elements; CMOS technology; Circuits; Design engineering; Design methodology; Flip-flops; Libraries; Power engineering and energy; Power supplies; Switches; Viterbi algorithm; Leakage; low power; power gating; semicustom; standard cell;
fLanguage :
English
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
Publisher :
ieee
ISSN :
1549-7747
Type :
jour
DOI :
10.1109/TCSII.2007.894414
Filename :
4237367
Link To Document :
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