• DocumentCode
    933928
  • Title

    Implementation of a Flexible LDPC Decoder

  • Author

    Masera, Guido ; Quaglio, Federico ; Vacca, Fabrizio

  • Author_Institution
    Politecnico di Torino, Turin
  • Volume
    54
  • Issue
    6
  • fYear
    2007
  • fDate
    6/1/2007 12:00:00 AM
  • Firstpage
    542
  • Lastpage
    546
  • Abstract
    Low-density parity-check codes (LDPC) are among the most powerful error correcting tools today available. For this reason they became very popular in several applications such as the digital satellite broadcasting system (DVB-S2), wireless local area network (IEEE 802.11n) and metropolitan area network (802.16e). Whereas several code-specific decoders have been proposed in the literature, the implementation of a high performance yet flexible LDPC decoder still is a challenging topic. This work presents a novel formulation of the decoding algorithm that strongly simplifies internal communication requirements and enables the development of decoders supporting generally defined LDPC codes. The resulting architecture is tailored to decode both IEEE 802.11n and IEEE 802.16e LDPC codes, as well as any other code of comparable complexity. The implementation cost deriving from the full flexibility offered by the proposed approach is also evaluated.
  • Keywords
    CMOS integrated circuits; VLSI; application specific integrated circuits; decoding; direct broadcasting by satellite; error correction codes; metropolitan area networks; parity check codes; wireless LAN; ASIC implementation; CMOS technology; DVB-S2; IEEE 802.11n; IEEE 802.16e; VLSI implementation; digital satellite broadcasting system; error correcting tools; flexible LDPC decoder; low-density parity-check codes; metropolitan area network; wireless local area network; Costs; Digital video broadcasting; Error correction codes; Hardware; Iterative algorithms; Iterative decoding; Parallel architectures; Parity check codes; Satellite broadcasting; Wireless LAN; Channel decoders; VLSI implementation; low-density parity-check code (LDPC); parallel architectures; reconfigurable architectures;
  • fLanguage
    English
  • Journal_Title
    Circuits and Systems II: Express Briefs, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    1549-7747
  • Type

    jour

  • DOI
    10.1109/TCSII.2007.894409
  • Filename
    4237370