DocumentCode :
933994
Title :
Secured Flipped Scan-Chain Model for Crypto-Architecture
Author :
Sengar, Gaurav ; Mukhopadhyay, Debdeep ; Chowdhury, Dipanwita Roy
Author_Institution :
Indian Inst. of Technol., Kharagpur
Volume :
26
Issue :
11
fYear :
2007
Firstpage :
2080
Lastpage :
2084
Abstract :
Scan chains are exploited to develop attacks on cryptographic hardware and steal intellectual properties from the chip. This paper proposes a secured strategy to test designs by inserting a certain number of inverters between randomly selected scan cells. The security of the scheme has been analyzed. Two detailed case studies of RC4 stream cipher and AES block cipher have been presented to show that the proposed strategy prevents existing scan-based attacks in the literature. The elegance of the scheme lies in its less hardware overhead.
Keywords :
cryptography; AES block cipher; RC4 stream cipher; crypto-architecture; secured flipped scan-chain model; steal intellectual properties; Automatic testing; Circuit testing; Computer science; Cryptography; Design for testability; Flip-flops; Hardware; Intellectual property; Registers; Security; Block ciphers; design_for_testability; hardware overhead; scan-chain-based attacks; scan_based_test; security margin; stream ciphers;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2007.906483
Filename :
4352010
Link To Document :
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