• DocumentCode
    934202
  • Title

    M3-a multilevel mixed-mode mixed A/D simulator

  • Author

    Chadha, Rakesh ; Visweswariah, Chandramouli ; Chen, Chin-Fu

  • Author_Institution
    AT&T Bell Lab., Murray Hill, NJ, USA
  • Volume
    11
  • Issue
    5
  • fYear
    1992
  • fDate
    5/1/1992 12:00:00 AM
  • Firstpage
    575
  • Lastpage
    585
  • Abstract
    A unified multilevel mixed-mode simulation capability for mixed analog/digital integrated circuits is described. First, a methodology for describing arbitrary analog or mixed analog/digital blocks at the behavioral level is proposed. In order to verify such models, a verification tool has been developed. The tools modgens and modgenz convert transfer functions H(s) and H(z), respectively, into state space representations in the time domain and generate behavioral models. Thus, the methodology allows digital, analog, and mixed analog/digital subcircuits to be described at various levels. While the analog portions of the circuit are simulated with high accuracy, the digital portions can be simulated in various models. Simulation is event-driven. For the behavioral analog models, block elimination with unique reordering and pivoting techniques are used to accommodate state variables. This capability has been integrated into the MOTIS3 design verification system. The simulation of representative mixed analog/digital simulation examples is described
  • Keywords
    application specific integrated circuits; circuit analysis computing; M3; MOTIS3 design verification system; behavioral analog models; behavioral level; block elimination; mixed analog/digital integrated circuits; mixed-mode simulation; multilevel mixed-mode mixed A/D simulator; reordering and pivoting techniques; verification tool; Capacitors; Circuit simulation; Computational modeling; Design automation; Discrete event simulation; Engines; Equations; Flexible printed circuits; Partitioning algorithms; Voltage;
  • fLanguage
    English
  • Journal_Title
    Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0278-0070
  • Type

    jour

  • DOI
    10.1109/43.127619
  • Filename
    127619