IC defect sensitivity for footprint-type spot defects

While it is important to exhaustively verify IC designs for their functional performance, it is equally important to verify their robustness against spot defects, that is, to foresee what will happen to the design when it is exposed to defect conditions in a real manufacturing environment. One such verification is done by extracting the layout sites where defects can induce a functional failure of the design. Initial attempts to perform this verification task were based on a `critical area extraction´ of one layer at a time, neglecting the electrical significance of interrelationships between layers. A novel method to construct deterministically multilayer critical areas is presented. These critical areas are established on the theoretical basis of defect semantics and on the new concept of `susceptible sites´. A system comprising several algorithms which in principle maintain simultaneously as many scan lines as the number of layers, in such a way that it is possible to keep track of the vertical and horizontal effects of defects, is developed