Abstract :
All possible bridging faults (BFs) between any two circuit nodes are considered, where a circuit node may be the drain, source, or gate terminal of a transistor. Several examples are given to show that under certain circumstances current supply monitoring (CSM) cannot give correct test results. A circuit partitioning model is described, and a minimal set of design and test rules is presented. This set of rules is minimal in the sense that if any one of these rules is removed, then circuits exist for which CSM cannot give correct test results. When all the rules are satisfied it can be formally shown that: (1) all signal irredundant BFs can be detected by single vector tests, and (2) a test vector that detects a single bridging fault f1 also detects all multiple BFs that contain f1. To enhance the applicability of CSM, test and/or design strategies for dealing with circuits that do not satisfy each rule are proposed. Such circuits include a special exclusive OR gate, BiCMOS circuits, domino logic, synchronous sequential circuits, and circuits implemented by the silicon on insulator (SOI) technology
Keywords :
CMOS integrated circuits; integrated circuit testing; logic testing; production testing; BiCMOS circuits; CMOS circuits; IDDQ testing; SOI circuits; bridging faults detection; circuit partitioning model; current supply monitoring; design strategies; domino logic; exclusive OR gate; minimal set of design rules; minimal set of test rules; single vector tests; synchronous sequential circuits; CMOS logic circuits; Circuit faults; Circuit testing; Current supplies; Electrical fault detection; Fault detection; Monitoring; Semiconductor device modeling; Sequential circuits; Silicon on insulator technology;
