Design methodology for stoppable clock systems

Many approaches have been developed for designing large, highly parallel computer systems. Classical synchronous approaches are susceptible to synchronisation problems at the clock pulse level. Newer asynchronous approaches, on the other hand, avoid such problems but are expensive to implement. This paper proposes a compromise approach that builds on the well developed synchronous system design techniques and, at the same time, avoids the clock pulse level synchronisation problems. In this approach, a system has a totally synchronous core with a ´stoppable´ clock and uses an asynchronous interface for external communication. With the clock not running, the asynchronous interface receives and sends information in the form of packets, setting up the proper input values and initial state for the synchronous core. The clock is then started, and the synchronous core behaves as a sequential state machine initialised to the proper state and subjected to the proper input values. When the core has finished its computation, the clock is stopped and the process is repeated. A methodology for building such systems is presented in the paper.