DocumentCode :
934742
Title :
Layout-blocking in behavioral patterns on chips
Author :
Zargham, Mehdi R.
Author_Institution :
Dept. of Comput. Sci., Southern Illinois Univ., Carbondale, IL, USA
Volume :
10
Issue :
4
fYear :
1991
Firstpage :
29
Lastpage :
33
Abstract :
The nature and role of VLSI CAD systems are examined. The fabrication and operation of MOS transistors and inverters, two basic components of VLSI circuits, are described. Layout level description of circuits is discussed, and automatic layout systems are considered. The placement and routing problems are also discussed.<>
Keywords :
MOS integrated circuits; VLSI; circuit layout CAD; logic gates; transistors; MOS inverters; MOS transistors; VLSI CAD systems; automatic layout systems; behavioral patterns; blocking; chips; layout level description; placement problems; routing problems; Circuits; Design automation; Graphics; Large scale integration; Layout; Logic design; MOSFETs; Physics; Switches; Very large scale integration;
fLanguage :
English
Journal_Title :
Potentials, IEEE
Publisher :
ieee
ISSN :
0278-6648
Type :
jour
DOI :
10.1109/45.127678
Filename :
127678
Link To Document :
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