Title :
CMOS stuck-open fault testability
Author :
Rajsuman, Rochit ; Malaiya, Yashwant K. ; Jayasumana, Anura P.
Author_Institution :
Dept. of Electr. Eng., Colorado State Univ., Fort Collins, CO, USA
Abstract :
CMOS combinational circuits exhibit sequential behavior in the presence of open faults, thus making it necessary to use two-pattern tests. An example which illustrates how such tests can be invalidated by glitches induced by circuit delays is presented. It is also shown that some results recently reported by researchers may not be valid in the presence of glitches.<>
Keywords :
CMOS integrated circuits; combinatorial circuits; integrated circuit testing; logic testing; CMOS combinational circuits; CMOS stuck-open fault testability; circuit delays; example; glitches; presence of open faults; sequential behavior; two-pattern tests; Circuit faults; Circuit simulation; Circuit testing; Computational modeling; Computer simulation; Delay; Electrons; Logic; Robustness; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
