Efficient architecture and hardware implementation of the Whirlpool hash function

The latest cryptographical applications demand both high speed and high security. In this paper, an architecture and VLSI implementation of the newest powerful standard in the hash families, Whirlpool, is presented. It reduces the required hardware resources and achieves high-speed performance. The architecture permits a wide variety of implementation tradeoffs. The implementation is examined and compared in the security level and in the performance by using hardware terms. This is the first Whirlpool implementation allowing fast execution, and effective substitution of any previous hash families´ implementations such as MD5, RIPEMD-160, SHA-1. SHA-2 etc, in any cryptography application.