Low-power multiplierless DCT architecture using image correlation

Low-power design is one of the most important challenges to maximize battery life in portable devices and to save the energy during system operation. In this paper, we propose a low-power DCT (discrete cosine transform) architecture using a modified multiplierless CORDIC (coordinate rotation digital computer) arithmetic. The switching power consumption is reduced during DCT: the proposed architecture does not perform arithmetic operations of unnecessary bits during the CORDlC calculations. The experiment results show that we can reduce up to 26.1% power dissipation without compromise of the final DCT results. Also, the speed of the proposed architecture is increased about 10%. The proposed low-power DCT architecture can be applied to consumer electronics and portable multimedia systems requiring high throughput and low-power.