Recursive addition and its parameterisation in VLSI

This paper describes the specification, simulation and implementation of a parallel addition algorithm based on the recursive methodology. The features of this recursive addition algorithm are regularity, modularity, local interconnections, intensive pipelining and concurrency which are advantageous in real-time signal processing. The recursivity of the approach to be described allows high-level addition structures to be parameterised and built into a silicon compilation environment which may facilitate design automation in VLSI signal processing. The algorithm has been proven thoroughly by a mixed-mode simulation which shows a favourable 155.5 ns worst case bandwidth at 1.56 W power dissipation for a 32-bit 5 ¿m NMOS version. Comparison of the recursive algorithm with carry lookahead addition (CLA), carry propagate addition (CPA), Brent/Kung CLA, conditional sum addition and carry select addition is in favour of the recursive addition at word sizes smaller or equal to 16. A close match between the algorithm complexity obtained from theory and the actual layout simulation statistics proves the validity of this methodology.