Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits

Author

Caffarena, Gabriel ; Constantinides, George A. ; Cheung, Peter Y K ; Carreras, Carlos ; Nieto-Taladriz, Octavio

Author_Institution

Dept. de Ingenieria Electron., Univ. Politecnica de Madrid, Spain

Volume

53

Issue

5

fYear

2006

fDate

5/1/2006 12:00:00 AM

Firstpage

339

Lastpage

343

Abstract

In this brief, we address the combined application of word-length allocation and architectural synthesis of linear time-invariant digital signal processing systems. These two design tasks are traditionally performed sequentially, thus lessening the overall design complexity, but ignoring forward and backward dependencies that may lead to cost reductions. Mixed integer linear programming is used to formulate the combined problem and results are compared to the two-step traditional approach.

Keywords

digital signal processing chips; integer programming; linear network synthesis; linear programming; architectural synthesis; cost reductions; digital signal processing circuits; fixed-point arithmetic; linear digital signal processing systems; mixed integer linear programming; time-invariant digital signal processing systems; word-length allocation; Algorithm design and analysis; Circuit synthesis; Costs; Delay; Digital signal processing; Fixed-point arithmetic; Hardware; Mixed integer linear programming; Signal processing algorithms; Signal synthesis; Architectural synthesis; digital signal processing; fixed-point arithmetic; word-length allocation;

fLanguage

English

Journal_Title

Circuits and Systems II: Express Briefs, IEEE Transactions on

Publisher

ieee

ISSN

1549-7747

Type

jour

DOI

10.1109/TCSII.2005.862175

Filename

1632340