• DocumentCode
    936
  • Title

    A 0.18- \\mu m CMOS Dual-Band Frequency Synthesizer With Spur Reduction Calibration

  • Author

    Yang-Wen Chen ; Yueh-Hua Yu ; Chen, Yi-Jan Emery

  • Author_Institution
    Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
  • Volume
    23
  • Issue
    10
  • fYear
    2013
  • fDate
    Oct. 2013
  • Firstpage
    551
  • Lastpage
    553
  • Abstract
    This letter presents a 0.18 μm CMOS dual-band frequency synthesizer with charge-pump current mismatch calibration to reduce reference spurs. To enhance calibration accuracy the high-resolution phase detector (HRPD) is incorporated in this work. The measured output spur level is less than -63 dBc after the calibration circuits are activated and the reference spur reduction is more than 5.6 dB throughout the whole frequency range. The frequency synthesizer draws 16 mA from a 1.8 V power supply, and the covered frequency bands are 5.18-5.32 GHz and 5.74-5.82 GHz.
  • Keywords
    CMOS integrated circuits; calibration; frequency synthesizers; CMOS dual-band frequency synthesizer; charge-pump current mismatch calibration; current 16 mA; frequency 5.18 GHz to 5.32 GHz; frequency 5.74 GHz to 5.82 GHz; high-resolution phase detector; size 0.18 mum; spur reduction calibration; voltage 1.8 V; CMOS integrated circuits; Calibration; Detectors; Dual band; Frequency synthesizers; Synthesizers; Voltage-controlled oscillators; Charge-pump (CP) current calibration; frequency synthesizer; phase-locked loop (PLL); spur suppression;
  • fLanguage
    English
  • Journal_Title
    Microwave and Wireless Components Letters, IEEE
  • Publisher
    ieee
  • ISSN
    1531-1309
  • Type

    jour

  • DOI
    10.1109/LMWC.2013.2279113
  • Filename
    6590031