Design and implementation of an RNS-based 2-D DWT processor

Author

Liu, Yong ; Lai, Edmund M K

Author_Institution

Sch. of Comput. Eng., Nanyang Technol. Univ., Singapore

Volume

50

Issue

1

fYear

2004

fDate

2/1/2004 12:00:00 AM

Firstpage

376

Lastpage

385

Abstract

Discrete wavelet transform has been incorporated as part of the JPEG2000 image compression standard and is used in many consumer imaging products. This paper presents a 2-dimensional biorthogonal DWT processor design based on the residue number system. The symmetric extension scheme is employed to reduce distortion at image boundaries. Hardware complexity reduction and utilization improvement are achieved by hardware sharing. Our implementation results show that the design is able to fit into a 1,000,000-gate FPGA device and is able to complete a first level 2-D DWT decomposition of a 32×32-pixel image in 205 μs.

Keywords

computational complexity; data compression; discrete wavelet transforms; field programmable gate arrays; image coding; processor scheduling; residue number systems; 2D DWT processor; FPGA device; JPEG2000 image compression standard; biorthogonal DWT processor design; complexity reduction; control units; data scheduling; discrete wavelet transform; field programmable gate array; filter banks; hardware sharing; image boundaries; residue number system arithmetic; symmetric extension scheme; utilization improvement; Application software; Discrete wavelet transforms; Dynamic range; Field programmable gate arrays; Filter bank; Finite impulse response filter; Hardware; Image coding; Signal analysis; Wavelet analysis;

fLanguage

English

Journal_Title

Consumer Electronics, IEEE Transactions on

Publisher

ieee

ISSN

0098-3063

Type

jour

DOI

10.1109/TCE.2004.1277887

Filename

1277887