Computer generation of topological equations and pseudocircuits for the self testing analogue fault diagnosis algorithm

This paper introduces methods of generating topological equations and pseudocircuits for the self-testing analogue fault diagnosis algorithm. The equations will be used to formulate the fault simulation model of the self-testing algorithm. The pseudocircuits constructed, on the other hand, will be used to conduct fault simulation by any circuit analysis program package. The proposed methods are applicable to both linear and nonlinear systems, disregarding the components included, which can be as simple as R, L, C or as complex as a replaceable chip or subsystem.