Title :
A 92-MHz 13-bit IF digitizer using optimized SC integrators in 0.35-μm CMOS technology
Author :
Thandri, Bharath Kumar ; Silva-Martinez, Jose
Author_Institution :
Analog & Mixed Signal Group, Texas A&M Univ., College Station, TX, USA
fDate :
5/1/2006 12:00:00 AM
Abstract :
A feedforward compensation scheme with no Miller capacitors is proposed to overcome the bandwidth limitations of traditional Miller compensation schemes. The technique has been used in the design of an operational transconductance amplifier (OTA) with a dc gain of 80 dB, gain bandwidth of 1.4 GHz, phase margin of 62°, and 2 ns settling time for 2-pF load capacitor in a standard 0.35-μm CMOS technology. The OTA´s current consumption is 4.6 mA. The OTA is used in the design of a fourth-order switched-capacitor bandpass ΣΔ modulator with a clock frequency of 92 MHz. It achieves a peak signal-to-noise ratio of 80 and 54 dB for 270-kHz (GSM) and 3.84-MHz (CDMA) bandwidths, respectively and consumes 19 mA of current from a ±1.25-V supply.
Keywords :
CMOS integrated circuits; analogue-digital conversion; integrating circuits; modulators; operational amplifiers; radiofrequency amplifiers; radiofrequency integrated circuits; switched capacitor networks; 0.35 micron; 1.25 V; 1.4 GHz; 13 bit; 19 mA; 2 ns; 2 pF; 270 kHz; 3.84 MHz; 4.6 mA; 80 dB; 92 MHz; CMOS technology; IF digitizer; Miller capacitors; SC integrators; analog-to-digital converter; bandpass sigma-delta modulator; feedforward compensation; operational transconductance amplifier; phase margin; pole-zero doublet; switched-capacitor bandpass SA modulator; Bandwidth; CMOS technology; Capacitors; Clocks; Frequency; GSM; Gain; Operational amplifiers; PSNR; Transconductance; Analog-to-digital converter (ADC); bandpass sigma–delta; feedforward compensation; pole–zero doublet;
Journal_Title :
Circuits and Systems II: Express Briefs, IEEE Transactions on
DOI :
10.1109/TCSII.2006.870217
