DocumentCode :
936174
Title :
Automatic test program generation: a case study
Author :
Corno, Fulvio ; Sànchez, Ernesto ; Reorda, Matteo Sonza ; Squillero, Giovanni
Author_Institution :
Politecnico di Torino, Italy
Volume :
21
Issue :
2
fYear :
2004
Firstpage :
102
Lastpage :
109
Abstract :
Design validation is a critical step in the development of present-day microprocessors, and some authors suggest that up to 60% of the design cost is attributable to this activity. Of the numerous activities performed in different stages of the design flow and at different levels of abstraction, we focus on simulation-based design validation performed at the behavioral register-transfer level. Designers typically write assertions inside hardware description language (HDL) models and run extensive simulations to increase confidence in device correctness. Simulation results can also be useful in comparing the HDL model against higher-level references or instruction set simulators. Microprocessor validation has become more difficult since the adoption of pipelined architectures, mainly because you can´t evaluate the behavior of a pipelined microprocessor by considering one instruction at a time; a pipeline´s behavior depends on a sequence of instructions and all their operands.
Keywords :
automatic test pattern generation; formal verification; genetic algorithms; hardware description languages; microprocessor chips; parallel architectures; automatic test program generation; behavioral register-transfer level; genetic algorithms; hardware description language; microprocessor validation; pipelined architectures; simulation-based design validation; Algorithms; Assembly; Automatic testing; Computer aided software engineering; Encoding; Evolutionary computation; Feedback; Genetic programming; Microprocessors; Pipelines;
fLanguage :
English
Journal_Title :
Design & Test of Computers, IEEE
Publisher :
ieee
ISSN :
0740-7475
Type :
jour
DOI :
10.1109/MDT.2004.1277902
Filename :
1277902
Link To Document :
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